1. Field of the Invention
The present invention generally relates to the art of microelectronic integrated circuits. In particular, the present invention relates to the art of calculating the capacitance of metal wires in integrated circuits.
2. Description of the Prior Art
An integrated circuit chip (hereafter referred to as an xe2x80x9cICxe2x80x9d or a xe2x80x9cchipxe2x80x9d) comprises cells and connections between the cells formed on a surface of a semiconductor substrate. The IC may include a large number of cells and require complex connections between the cells.
A cell is a group of one or more circuit elements such as transistors, capacitors, and other basic circuit elements grouped to perform a function. Each of the cells of an IC may have one or more pins, each of which, in turn, may be connected to one or more other pins of the IC by wires. The wires connecting the pins of the IC are also formed on the surface of the chip.
A net is a set of two or more pins which must be connected. Because a typical chip has thousands, tens of thousands, or hundreds of thousands of pins which must be connected in various combinations, the chip also includes definitions of thousands, tens of thousands, or hundreds of thousands of nets, or sets of pins. All the pins of a net must be connected. The number of the nets for a chip is typically in the same order as the order of the number of cells on that chip. Commonly, a majority of the nets include only two pins to be connected; however, many nets comprise three or more pins. Some nets may include hundreds of pins to be connected. A netlist is a list of nets for a chip.
Microelectronic integrated circuits consist of a large number of electronic components that are fabricated by layering several different materials on a silicon base or wafer. The design of an integrated circuit transforms a circuit description into a geometric description which is known as a layout. A layout consists of a set of planar geometric shapes in several layers.
The layout is then checked to ensure that it meets all of the design requirements. The result is a set of design files in a particular unambiguous representation known as an intermediate form that describes the layout. The design files are then converted into pattern generator files that are used to produce patterns called masks by an optical or electron beam pattern generator.
During fabrication, these masks are used to pattern a silicon wafer using a sequence of photolithographic steps. The component formation requires very exacting details about geometric patterns and separation between them. The process of converting the specifications of an electrical circuit into a layout is called the physical design.
Due to the large number of components and the exacting details required by the fabrication process, physical design is not practical without the aid of computers. As a result, most phases of physical design extensively use Computer Aided Design (CAD) tools, and many phases have already been partially or fully automated. Automation of the physical design process has increased the level of integration, reduced turn around time and enhanced chip performance.
The objective of physical design is to determine an optimal arrangement of devices in a plane or in a three dimensional space, and an efficient interconnection or routing scheme between the devices to obtain the desired functionality.
An exemplary integrated circuit chip is illustrated in FIG. 1 and generally designated by the reference numeral 26. The circuit 26 includes a semiconductor substrate 26A on which are formed a number of functional circuit blocks that can have different sizes and shapes. Some are relatively large, such as a central processing unit (CPU) 27, a read-only memory (ROM) 28, a clock/timing unit 29, one or more random access memories (RAM) 30 and an input/output (I/O) interface unit 31. These blocks, commonly known as macroblocks, can be considered as modules for use in various circuit designs, and are represented as standard designs in circuit libraries.
The integrated circuit 26 further comprises a large number, which can be tens of thousands, hundreds of thousands or even millions or more of small cells 32. Each cell 32 represents a single logic element, such as a gate, or several logic elements interconnected in a standardized manner to perform a specific function. Cells that consist of two or more interconnected gates or logic elements are also available as standard modules in circuit libraries.
The cells 32 and the other elements of the circuit 26 described above are interconnected or routed in accordance with the logical design of the circuit to provide the desired functionality. Although not visible in the drawing, the various elements of the circuit 26 are interconnected by electrically conductive lines or traces that are routed, for example, through vertical channels 33 and horizontal channels 34 that run between the cells 32.
The input to the physical design problem is a circuit diagram, and the output is the layout of the circuit. This is accomplished in several stages including partitioning, floor planning, placement, routing and compaction.
1. Partitioning.
A chip may contain several million transistors. Layout of the entire circuit cannot be handled due to the limitation of memory space as well as the computation power available. Therefore, the layout is normally partitioned by grouping the components into blocks such as subcircuits and modules. The actual partitioning process considers many factors such as the size of the blocks, number of blocks and number of interconnections between the blocks.
The output of partitioning is a set of blocks, along with the interconnections required between blocks. The set of interconnections required is the netlist. In large circuits, the partitioning process is often hierarchical, although non-hierarchical (e.g. flat) processes can be used, and at the topmost level a circuit can have between 5 to 25 blocks. However, greater numbers of blocks are possible and contemplated. Each block is then partitioned recursively into smaller blocks.
2. Floor Planning and Placement.
This step is concerned with selecting good layout alternatives for each block of the entire chip, as well as between blocks and to the edges. Floor planning is a critical step as it sets up the ground work for a good layout. During placement, the blocks are exactly positioned on the chip. The goal of placement is to find a minimum area arrangement for the blocks that allows completion of interconnections between the blocks. Placement is typically done in two phases. In the first phase, an initial placement is created. In the second phase, the initial placement is evaluated and iterative improvements are made until the layout has minimum area and conforms to design specifications.
3. Routing.
The objective of the routing phase is to complete the interconnections between blocks according to the specified netlist. First, the space not occupied by blocks, which is called the routing space, is partitioned into rectangular regions called channels. The goal of a router is to complete all circuit connections using the shortest possible wire length and using only the channel.
Routing is usually done in two phases referred to as the global routing and detailed routing phases. In global routing, connections are completed between the proper blocks of the circuit disregarding the exact geometric details of each wire and terminal. For each wire, a global router finds a list of channels that are to be used as a passageway for that wire. In other words, global routing specifies the loose route of a wire through different regions of the routing space.
Global routing is followed by detailed routing which completes point-to-point connections between terminals on the blocks. Loose routing is converted into exact routing by specifying the geometric information such as width of wires and their layer assignments. Detailed routing includes the exact channel routing of wires.
The floor space on ASICs are divided into small areas by grid lines. The grid lines are usually horizontal and vertical lines that divide the floor space on ASICs into small rectangular (usually square) areas. A grid based router usually places circuit elements on the grid lines. In certain cases, a circuit element may be placed off the grid lines.
FIG. 2 provides a simplified cross-sectional view of a typical integrated circuit chip (or die) 50. As shown in FIG. 2, chip 50 includes a semiconductor substrate 59, metal layers 51 to 54, electrically insulating layers 56, and passivation layer 58. Semiconductor substrate 59, which is typically polysilicon, is used for forming the transistors and other electronic devices.
Metal layers 51 to 54 may be formed from any of a variety of materials including aluminum, copper or an electrically conductive alloy. Typically, two to six metal layers are formed on top of substrate 59. Between metal layers 51 and 52, 52 and 53, and 53 and 54, and between metal layers 51 and substrate 59 is an electrically insulating layer 56, which typically is formed as an oxide film. Connections between any of metal layers 51 to 54 and semiconductor substrate 59 are made using interlayer holes called vias. Passivation layer 58 functions to prevent the deterioration of the electrical properties of the die caused by water, ions and other external contaminants, and typically is made of a scratch-resistant material such as silicon nitride and/or silicon dioxide. In a typical circuit, the wires on the metal layer 51 would be orthogonal to the wires on the metal layer 52, the wires on the metal layer 52 would be orthogonal to the wires on the metal layer 53, and the wires on the metal layer 53 would be orthogonal to the wires on the metal layer 54.
Throughout the design process, designers need to know the performance of the final layout. In order to know the final performance, designers need to know the interconnect delays caused by parasitic capacitances such as wiring capacitances caused by metal wires. Basically, accurate and fast capacitance extraction is essential to accurate delay, power and signal integrity calculation. Therefore, ASIC designers need to perform capacitance extraction on the circuit layout to determine the total capacitance and the interconnect delay.
In prior art, designers performed a 2-D or 3-D field solution on the circuit layout to conduct capacitance extraction. Although such field solution test is accurate, 2-D or 3-D field solution tests require much memory and time to conduct. In other instances, designers first formed a large library of patterns and model capacitances based on the geometry of various wires and inter-wire spacings. The designers then performed capacitance extractions on circuit layouts based on the library of patterns and model capacitances. Although such test does not require as much memory or time as the 2-D or 3-D field solution tests, the test requires a library with numerous characterizations and may not produce an accurate result that justifies the effort of building a large library.
It is an object of the present invention to provide methods for calculating a capacitance of a metal wire in an integrated circuit, which obviate for practical purposes the above mentioned limitations.
According to an embodiment of the present invention, the capacitances of metal wires in IC circuits are calculated by first creating a library containing tables with capacitive values for various predetermined wiring topologies. The library is created by conducting capacitance simulations on various wiring topologies including single-grid on-grid configurations, off-grid configurations and configurations with wide metal lines. Based on the capacitance simulations, each of the predetermined wiring topologies has an associated capacitive value. After creating the library, the preferred embodiments of the present invention calculate the total capacitance of a metal wire by extracting a layout topology of a segment of the metal wire. The extracted layout topology is then converted to a mapped topology based on certain rules. The mapped topology is used to reference the library to find one of the predetermined wiring topologies that matches or corresponds to the mapped topology. The associated capacitive value is then extracted from the corresponding predetermined wiring topology. The extracted capacitive value is then used to calculate a part of the total capacitance of the metal wire. The process is repeated for other segments of the metal wire.
Other features and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings which illustrate, by way of example, various features of embodiments of the invention.